The invention provides a data processing system comprising at least two computers which are coupled to a common bus, one said computer being a master which controls at least one further computer as a slave. Provision of such a configuration enables the individual computers to operate fully simultaneously and asynchronously, independently of each other, without mutual synchronization being required during the transmission of data, such mutual synchronization being required, for example, in a known (see below) data processing system including a common bus for a plurality of microcomputers. As a result, the utilization of the system can be improved. Furthermore, in such a system it can be arranged that each microcomputer can have available substantially the whole of its address space, as opposed to another known (see below) data processing system having a common memory for a plurality of microcomputers. Availability of the complete address space exists in a conventional data processing system comprising a common bus for a plurality of microcomputers, but comparatively complex input/output interfaces between the common bus and the individual microcomputers are required therein. Moreover, provision of such a configuration enables a high transmission rate to be achieved when a plurality of simultaneous data transmissions occur; thus this speed can be roughly comparable with that of a data processing system having a common memory for a plurality of microcomputers. Thus, provision of such a configuration enables the advantages of a data processing system including a common bus for a plurality of microcomputers and the advantages of a system having a common memory for a plurality of microcomputers to be combined Data processing systems of the said two known kinds are described, for example, in the article "Four design principles get the most out of microprocessor systems," Electronics, Jan. 20, 1977, pages 102 to 110, notably with reference to FIGS. 8 and 9 of this article.
If the system includes a plurality of slaves, it can be an advantage if the address space of the master is capable of accommodating the address spaces of all buffer memories. Transmission of data between two slaves can then be particularly simple, because the master can then have available in its address space the buffer memories of both slaves involved in the data transmission, so that the data transmission can take place from one buffer memory to the other without intermediate storage.
It can also be an advantage if the transmission of data from and/or to said buffer memory via the common bus takes place via a direct memory access unit which gains access to the common bus. Provision of such a unit can enable the transmission speed of the data to be increased.
Status signals transmitted via the input/output interfaces may control the master or the relevant slave by interrupting a program sequence presently being carried out therein. If this is so delay times can be reduced and the load on the relevant computer can be reduced.